1. Field of the Invention
The present invention relates generally to test auxiliary circuits, and more particularly, to test auxiliary circuits employed for testing semiconductor memory devices.
2. Description of the Prior Art
FIG. 1 is a diagram showing structure of a conventional scan-path used as a test auxiliary circuit for performing operation tests of a semiconductor device such as a RAM (Random Access Memory).
The scan-path comprises n scan registers 14 connected in series. Each of the scan registers 14 comprises a first clock terminal 5, a second clock terminal 6, a selector control terminal 8, a serial input terminal 9, a parallel input terminal 10, a parallel output terminal 11 and a serial output terminal 12. The serial output terminal 12 of each of the scan registers 14 is connected to the serial input terminal 9 of an adjacent scan register 14. The selector control terminals 8 of the n scan registers 14 are connected to each other to receive a common select signal SEL. The first clock terminals 5 and the second clock terminals 6 of the scan registers 14 are connected to each other to receive a common first clock signal CK1 and a common second clock signal CK2, respectively.
The scan-path performs a serial shift operation or a parallel shift operation in response to the select signal SEL. When the serial shift operation is selected by the select signal SEL, data SI applied to the serial input terminal 9 of the scan register 14 in the first stage (shown at the left end in FIG. 1) is sequentially shifted to the scan registers 14 in the subsequent stages in synchronzation with the first and second clock signals CK1 and CK2 (a two-phase clock), to be sequentially outputted as serial output data SO from the serial output terminal 12 of the scan register 14 in the final stage (as shown at the right end in FIG. 1). On the other hand, when the parallel shift operation is selected by the select signal SEL, data PI applied to the parallel input terminals 10 are latched in the scan registers 14 in synchronization with the first and second clock signals CK1 and CK2, and outputted from the parallel output terminals 11.
In general, the scan-paths are connected to input terminals and output terminals of a circuit under test, respectively. Test data can be shifted in the scan-path connected to the input terminals of the circuit under test from the serial input terminal 9 by the serial shift operation and then, inputted to the circuit under test from the parallel output terminals 11 by the parallel shift operation. In addition, response data corresponding to the test data, obtained by the circuit under test can be accepted in the scan-path connected to the output terminals of the circuit under test from the parallel input terminals 10 by the parallel shift operation and then, derived from the serial output terminal 12 by the serial shift operation. In an example shown in FIG. 1, external pins required for testing are only five pins of the first and second clock terminals 5 and 6, the selector control terminal 8, the serial input terminal 9 and the serial output terminal 12. Thus, in a system employing a scan-path, if the number n of scan registers is large, the number of external pins required for testing can be reduced, as compared with a system in which parallel data is directly drawn out to the external pins. Therefore, the scan-path is employed as a test auxiliary circuit.
FIG. 2 is a diagram showing circuit structure of each of the scan registers 14 in the scan-path shown in FIG. 1.
The scan register 14 comprises a first latch circuit 1a, a second latch circuit 1b and a selector circuit 7, and operates by a two-phase clock. The selector circuit 7 has a first input terminal a connected to a serial input terminal 9, a second input terminal b connected to a parallel input terminal 10, a control terminal c connected to a selector control terminal 8 and an output terminal d. The first latch circuit 1a has an input terminal D connected to the output terminal d of the selector circuit 7, an enable terminal EN connected to a first clock terminal 5 and an output terminal Q. The second latch circuit 1b has an input terminal D connected to the output terminal Q of the first latch circuit 1a, an enable terminal EN connected to a second clock terminal 6 and an output terminal Q connected to a parallel output terminal 11 and a serial output terminal 12. Either one of the serial input terminal 9 and the parallel input terminal 10 is selected in response to a select signal SEL, so that data in the selected input terminal is applied to the input terminal D of the first circuit 1a through the output terminal d. Data applied to the input terminal D is latched in the latch circuit 1 a in response to a first clock signal CK1, and outputted from the output terminal Q. Thereafter, the data latched in the first latch circuit 1a is latched in the second latch circuit 1b in response to a second clock signal CK2, and outputted from the output terminal Q.
Thus, the two-phase clock is applied to the first and second clock terminals 5 and 6, so that data applied to the serial input terminal 9 or the parallel input terminal 10 can be transferred to the serial output terminal 12 and the parallel output terminal 11, whereby a 1-bit shift operation is performed.
Thus, n scan registers 15 shown in FIG. 1 are connected in series, thereby forming a scan-path.
FIG. 3 is a circuit diagram showing another example of the conventional scan-path employed as a test auxiliary circuit.
The scan-path comprises n scan registers 15 connected in series. Each of the scan registers 15 comprises a parallel clock terminal 5a, a serial clock terminal 5b, a second clock terminal 6, a serial input terminal 9, a parallel input terminal 10, a parallel output terminal 11 and a serial output terminal 12. The serial output terminal 12 of each of the scan registers 15 is connected to the serial input terminal 9 of an adjacent scan register 15. The parallel clock terminals 5a of the n scan registers 15 are connected to each other to receive a common parallel clock signal PCK1, and the serial clock terminals 5b thereof are connected to each other to receive a common serial clock signal SCK1. In addition, the second clock terminals 6 of the scan registers 15 are connected to each other to receive a common second clock signal CK2. The scan-path performs a parallel shift operation when the clock signal PCK1 is applied to the parallel clock terminals 5a while performing a serial shift operation when the clock signal SCK1 is applied to the serial clock terminals 5b.
FIG. 4 is a diagram showing circuit structure of each of the scan registers 15 in the scan-path shown in FIG. 3.
The scan register 15 is formed by an MOS circuit, which comprises a first ratio-type latch circuit 1c, a second ratio-type latch circuit 1d and three N channel transistors 13a, 13b and 13c. Each of the first and second ratio-type latch circuits 1c and 1d comprises two NOT circuits. An input terminal p of the ratio-type latch circuit 1c is connected to a parallel input terminal 10 through the transistor 13a, and to a serial input terminal 9 through the transistor 13b. The transistor 13a has its gate connected to a parallel clock terminal 5a, and the transistor 13b has its gate connected to a serial clock terminal 5b. The transistor 13c is connected between an output terminal q of the ratio-type latch circuit 1c and an input terminal p of the second ratio-type latch circuit 1d, and has its gate connected to a second clock terminal 6.
When a clock signal PCK1 is applied to the parallel clock terminal 5a, the transistor 13a is turned-on, so that data PI applied to the parallel input terminal 10 is latched in the first ratio-type latch circuit 1c. Contrary to this, when a clock signal SCK1 is applied to the serial clock terminal 5b, the transistor 13b is turned on, so that data SI applied to the serial input terminal 9 is latched in the first ratio-type latch circuit 1c. This operation corresponds to a latch operation by the select signal SEL and the first clock signal CK1 in the scan register 14 shown in FIG. 2. Thus, data applied to the selected one of the parallel input terminal 10 and the serial input terminal 9 can be latched. Thereafter, when a second clock signal CK2 is applied to the second clock terminal 6, data latched in the first ratio-type latch circuit 1c is latched in the second ratio-type latch circuit 1d, and outputted to a parallel output terminal 11 and a serial output terminal 12.
Thus, a two-phase clock is applied to the parallel clock terminal 5a and the second clock terminal 6 or the serial clock terminal 5b and the second clock terminal 6, so that data applied to the parallel input terminal 10 or the serial input terminal 9 can be transferred to the parallel output terminal 11 and the serial output terminal 12, whereby a 1-bit shift operation can be performed. Thus, n scan registers 15 are connected in series, thereby forming the scan-path shown in FIG. 3.
FIG. 5 is a diagram showing an example of a case in which a scan-path is connected to a data output terminal of a RAM. In this case, a circuit under test is the RAM.
The scan-path comprises n scan registers 16 connected in series. Each of the scan registers 16 corresponds to each of the scan registers 14 or each of the scan registers 15 shown in FIGS. 1 to 4. A RAM 17 has n data output terminals 18. A parallel input terminal 10 of each of the scan registers 16 is connected to a corresponding data output terminal 18 of the RAM 17. In general, the scan-path is formed on the same semiconductor chip as that on which the RAM 17 is formed.
In general, when tests of the RAM are performed, data "0" or "1" are written to all addresses in the RAM and the data as written are read out. For example, data "0" are written to all addresses in the RAM 17 and the data as written are read out from all the addresses. Then, data "1" are written to all addresses in the RAM and the data as written are read out from all the addresses. If all of the data as written and the data as read out coincide with each other, it is determined that the RAM is an acceptable or nodefective product. Contrary to this, if any of the data as written and the data as read out do not coincide with each other, it is determined that the RAM is a defective product. In FIG. 5, the scan-path is employed for reading out data in the RAM 17 at the time of the above described tests.
Output data Q.sub.1 to Q.sub.n from the data output terminals 18 of the RAM 17 are accepted in the scan-path from parallel input terminals 10 by a parallel shift operation while being read out bit by bit from a serial output terminal 12 by a serial shift operation. Quality is determined by a testing device in response to the data as read out. This operation is performed with respect to all the addresses.
In the above described conventional test auxiliary circuit, even when data "0" or "1" are continuously read out as at the time of testing the RAM, a serial shift operation must be performed for every one read operation. Therefore, if the number of bits of data is large, i.e., n is large, the test time is increased.